1. Field of the Invention
The present invention relates to a semiconductor system including a plurality of memory systems, such as SRAMs, ROMs, and the like.
2. Description of the Prior Art
A conventional structure of a semiconductor system which includes a plurality of memory systems, circuit systems, or the like, is described below.
For example, an additional circuit, such as a level shifter, or the like, is provided or complicated well separation, or the like, is formed because the level of the supply voltage on a chip is not only one level and, specifically, it is necessary to provide three or more levels of supply voltages on the same chip (see, for example, Japanese Unexamined Patent Publication No. 2001-44295 (pp. 2–7, FIG. 1)). In the case of including a system which requires a high voltage for circuit operation, such as a flash memory, or the like, a high breakdown voltage gate oxidation film process is added to a standard process which is necessary for forming a logic device (see, for example, Japanese Unexamined Patent Publication No. 2003-7863 (pp. 2–7, FIG. 1)). Specifically, assuming that, for example, a logic section requires 1.0 V, a flash memory requires 3.0 V, and a DRAM requires 2.5 V, a gate oxide film, or the like, is formed in each of these elements to withstand the required voltage.
In the case where numerous types of memory devices and analog devices are incorporated in a single chip, it is estimated that more than five levels of optimum voltages are required as miniaturization advances in the future. Accordingly, more than five types of gate oxide films are required. It is extremely difficult to form such a device through the same process. That is, it is difficult to realize such a device with the conventional techniques disclosed in the above publications.
As an alternative technique, providing numerous levels of threshold voltages instead of providing various types of gate oxide films can be considered. However, in this case, the possibility of an off leak current due to an excessively low threshold voltage of a transistor and the possibility of a gate leak current due to an excessively thin gate oxidation film increase.
Further, as shown in FIG. 15, the threshold voltage differs among systems due to device miniaturization depending on the device layout, such as channel width, separation width, etc. Especially, since an SRAM, ROM, DRAM, and the like, use a very small device, the threshold voltages of systems are different even if the systems are produced through the same process. Thus, it is difficult to satisfy the leak current requirements in all of the memories. Since an analog circuit, or the like, uses a large device, it is extremely difficult to satisfy the leak current requirements in the analog circuit while satisfying the leak current requirements in all memory devices. In the example of FIG. 15, the threshold voltage is different among systems by 200 mV. For example, adjusting the threshold voltage of each system by ion implantation through a production process can be considered. However, in many cases, more than 10 levels of threshold voltages (n-channel and p-channel) have to be adjusted. This is, practically, almost impossible in view of the actual production cost.
In many semiconductor systems, the supply voltage and the clock frequency are controlled according to the amount of task processing, the task status in operation, on standby, or the like, or the system temperature. Thus, the specifications of the leak current differ depending on the circumstances. Therefore, it is necessary to flexibly change control of the leak current according to the operation environment of the system. However, it is difficult to follow variations in the operation environment of the entire system only by process adjustments and/or only with a leak reduction circuit provided to each memory. As a result, the requirements as to the off leak current and gate leak current cannot be satisfied.